1. Field of the Invention
The present invention generally relates to a thin film transistor array (TFT array), and more particularly, to a thin film transistor array capable of raising a uniformity of brightness.
2. Description of Related Art
A significant advance of a multimedia society benefits a considerable development of semiconductor devices and display devices. Furthermore, in the display devices' field, the thin film transistor array with advantages of high image quality, high compactness, low power consumption and free radiation have become a main stream of the market.
The thin film transistor liquid crystal display comprises the thin film transistor array, colour filters and a liquid crystal layer. FIG. 1 shows a top view of a conventional thin film transistor array. Referring to FIG. 1, the thin film transistor array 100 comprises a plurality of pixels 110 arranged in an array, wherein each pixel structure 110 consists of a scan line 112, a data line 114, a thin film transistor 116 and a pixel electrode 118 disposed in corresponding to the thin film transistor 116.
Referring to FIG. 1, the thin film transistor 116 is used as a switch element of each pixel structure 110 while the scan line 112 and the data line 114 are used to provide the selected pixel structure 110 with proper operating voltages for respectively driving the selected pixel structure 110 to display an image.
FIG. 2 shows a schematic equivalent circuit diagram of one pixel of a conventional thin film transistor liquid crystal display. Referring to FIG. 2, the pixel of a conventional thin film transistor liquid crystal display generally comprises a thin film transistor, a liquid crystal capacitance CLC and a storage capacitor CST.
Referring to FIG. 1 and FIG. 2 concurrently, the liquid crystal capacitor CLC is constituted by a coupling between the pixel electrode 118 in the thin film transistor array 100 and a common electrode (not shown) disposed on the colour filter. In addition, the storage capacitor CST is disposed on the thin film transistor array 100 and electrically connected to the liquid crystal capacitor CLC and the scan line 112. Besides, the gate G, the sources S and the drain D of the thin film transistor 116 are electrically connected to the scan line 112, the data line 114 and the liquid crystal capacitor CLC of the pixel electrode 118, respectively. Moreover, since there is an overlapped area between the gate G and the drain D, there exists a parasitic capacitance Cgd between the gate G and the drain D.
Referring to FIG. 1 and FIG. 2 concurrently again, since there exists a specific relationship between a voltage applied the liquid crystal capacitor CLC (i.e. a voltage applied to the pixel electrode 118 and the common electrode) and a light transmittance of liquid crystal molecules, a predetermined image can be displayed by controlling the voltage applied the liquid crystal capacitor CLC in accordance with the desired predetermined image. In addition, when the thin film transistor 116 is off, the voltage of the liquid crystal capacitor CLC is kept a constant value (i.e. at a holding state). However, as there exists the parasitic capacitance Cgd between the gate G and the drain D, the holding voltage of the liquid crystal capacitor CLC varies in accordance with signal variation of the data line 114 (i.e. so called coupling effect), thereby causing the holding voltage of the liquid crystal capacitor CLC deviates its predetermined value. This voltage variation is called a feed-through voltage ΔVP, which is expressed as the following:
                              Δ          ⁢                                          ⁢                      V            p                          =                                            C              gd                                                      C                gd                            +                              C                st                            +                              C                LC                                              ⁢          Δ          ⁢                                          ⁢                      V            g                                              (        1        )            Wherein ΔVg is amplitude of a pulse voltage applied the scan line 112.
Among current exposure processes for fabricating the thin film transistor array disposed on a substrate, most use a stepper to form shots in the panel. In other words, the thin film transistor array's pattern is composed of the shots formed by the stepper. Therefore, a stepper's position deviation resulting from its moving causes positions of patterns formed by each exposure shot to be deviated during each exposure period. Specifically, when an overlapped area between the gate G and the source S (shown in FIG. 1) of the thin film transistor 116 is different for every neighbour shots, which causes the parasitic capacitance Cgd (capacitance between the gate G and the source S) in each exposure shot to be different.
To solve the above mentioned problem, a conventional thin film transistor array is provided, which is shown in FIG. 3. Referring to FIG. 3, the conventional thin film transistor array's drains are designed to have a T shape so as to reduce the possible generated overlapped area R1 between the drain and the gate to be W×X, thereby further reducing parasitic capacitance variations in each exposure shot.
In addition, another solution to solve mentioned problem is to exploit a obscuring design added between different exposure shots to reduce a shot mura (referred to a variety of trace phenomena caused by a non-uniform brightness) occurred at boundary of the exposure shots. However, when exposure precision deviation is too large, the above two solutions still can't effectively improve a non-uniformity brightness problem caused by masks' shift-error.